Our first class was last Saturday.
Was able to modify the logic simulator to support Boolean Board.
https://github.com/hneemann/Digital/
Works great, generates VHDL or Verilog and the constraint file
Which runs through Vivado and downloads to the Boolean Board.
Did some simple schematics including user specified clock speed.
Am looking at this approach as a way to bypass the VHDL or Verilog
learning curve (generate RTL, look at it, modify, repeat.
The class is a mixture of college, high school and continuing
education students.
